Discrete-time control systems (2nd ed.)
Discrete-time control systems (2nd ed.)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Managing power consumption in networks on chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
ACM Transactions on Architecture and Code Optimization (TACO)
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Coordinated, distributed, formal energy management of chip multiprocessors
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
Proceedings of the 2006 international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Temperature-constrained power control for chip multiprocessors with online model estimation
Proceedings of the 36th annual international symposium on Computer architecture
Proceedings of the 46th Annual Design Automation Conference
Custom feedback control: enabling truly scalable on-chip power management for MPSoCs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Feedback control for providing QoS in NoC based multicores
Proceedings of the Conference on Design, Automation and Test in Europe
OS-level power minimization under tight performance constraints in general purpose systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Recovery-based design for variation-tolerant SoCs
Proceedings of the 49th Annual Design Automation Conference
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Energy-efficient multicore chip design through cross-layer approach
Proceedings of the Conference on Design, Automation and Test in Europe
Sensor-wise methodology to face NBTI stress of NoC buffers
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
Proceedings of the 50th Annual Design Automation Conference
Sliding-mode control to compensate PVT variations in dual core systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation problems in future multiprocessor systems-on-chip (MPSoCs). In this architecture, communication within each island is synchronous, while communication across different islands is achieved via mixed-clock, mixed-voltage queues. In order to dynamically control the speed of each domain in the presence of parameter and workload variations, we propose a robust feedback control methodology. Towards this end, we first develop a state-space model based on the utilization of the inter-domain queues. Then, we identify the theoretical conditions under which the network is controllable. Finally, we synthesize state feedback controllers to cope with workload variations and minimize power consumption. Experimental results demonstrate robustness to parameter variations and more than 40% energy savings by exploiting workload variations through dynamic voltage-frequency scaling (DVFS) for a hardware MPEG-2 encoder design.