Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
Application adaptive energy efficient clustered architectures
Proceedings of the 2004 international symposium on Low power electronics and design
A switch architecture and signal synchronization for GALS system-on-chips
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hardware based frequency/voltage control of voltage frequency island systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
Proceedings of the 45th annual Design Automation Conference
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of voltage/frequency island-based systems using hardware-based methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Dynamic instruction cascading on GALS microprocessors
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Integration, the VLSI Journal
Journal of Computer and System Sciences
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.01 |
This paper presents a low-latency FIFO design that interfaces subsystems on a chip working at different speeds. First, a single-clock domain design is introduced, which is then used as a basis for a mixed-clock version. Finally, the design is adapted to work between subsystems with very long interconnection delays. The designs can be made arbitrarily robust with regard to metastability and clock frequencies.