Mean Value Analysis for Blocking Queueing Networks
IEEE Transactions on Software Engineering
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A system level memory power optimization technique using multiple supply and threshold voltages
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
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System on Chip interconnects require first-in first-out buffers (FIFOs) to handle different data rates between IP cores. The design of an interconnect channel containing multiple stages of FIFO require making tradeoff between throughput and power consumption. The design variables are the sizes of the FIFOs, their voltages and their clock frequencies. Decreasing the FIFO clock frequencies saves power but it causes the channel performance (throughput) to decrease. In this work, we recover the performance by resizing the FIFOs in the channel. The voltage and clock scaling in the interconnect channel followed by FIFO resizing approach leads to significant power savings. The power savings is a function of system parameters λ (expected data production rate) and μ (expected data consumption rate). We observed a maximum dynamic power savings of 45.8%, 28.9% and 11.3% for min(λ, μ) of 0.2, 0.5 and 0.8 respectively. Our approach of reducing voltage in the interconnect channel will reduce the leakage power as well.