Mean Value Analysis for Blocking Queueing Networks
IEEE Transactions on Software Engineering
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Silicon trends and limits for advanced microprocessors
Communications of the ACM
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect scaling implications for CAD
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Latency-insensitive interconnects require first-in-first-out buffers (FIFO) for flow-control and storage. Interconnect delays are not scaling in proportion to the clock period and hence multiple stages of FIFOs will be needed for high performance interconnects. FIFOs in the interconnect are a significant contributor to the total power consumption. In this work, we propose a design methodology to synthesize a low power interconnect channel containing series connected FIFOs for latency-insensitive systems. Our approach is the first to consider and simultaneously optimize the channel clock frequency, voltage and the FIFO sizes to minimize the power consumption. For small problem size, we show that our approach finds solutions which are close to optimal. The power aware interconnect channel synthesis is affected by the system parameters like the data production rate and data consumption rate. The choice of optimal channel clock frequency, voltage and FIFO sizes can lead to power savings as high as 77.7%, 83.6% and 87% for a 3 stage, 4 stage and a 5 stage channel respectively.