Communications of the ACM
Low power design in deep submicron electronics
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
ICCD '98 Proceedings of the International Conference on Computer Design
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Coping with Latency in SOC Design
IEEE Micro
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A critical analysis of application-adaptive multiple clock processors
Proceedings of the 2003 international symposium on Low power electronics and design
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Proceedings of the 2003 international symposium on Low power electronics and design
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A switch architecture and signal synchronization for GALS system-on-chips
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Integration, the VLSI Journal
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compositionality of Statically Scheduled IP
Electronic Notes in Theoretical Computer Science (ENTCS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Mitigating the impact of variability on chip-multiprocessor power and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Architecture and Code Optimization (TACO)
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting process variability in voltage/frequency control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents several low-latency mixed-timing FIFO designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The design are then adapted to work between systems with very long interconnection delays, by migrating a single-clock solution by Carloni et al. (for “latency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.