Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Coordinated, distributed, formal energy management of chip multiprocessors
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DBmbench: fast and accurate database workload representation on modern microarchitecture
CASCON '05 Proceedings of the 2005 conference of the Centre for Advanced Studies on Collaborative research
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Power management of variation aware chip multiprocessors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Accomodating Diversity in CMPs with Heterogeneous Frequencies
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors
Proceedings of the 6th ACM conference on Computing frontiers
Thread motion: fine-grained power management for multi-core systems
Proceedings of the 36th annual international symposium on Computer architecture
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Optimal speed scaling under arbitrary power functions
ACM SIGMETRICS Performance Evaluation Review
TAPE: thermal-aware agent-based power economy for multi/many-core architectures
Proceedings of the 2009 International Conference on Computer-Aided Design
Performance and power consumption modeling for green COTS software router
COMSNETS'09 Proceedings of the First international conference on COMmunication Systems And NETworks
A model to exploit power-performance efficiency in superscalar processors via structure resizing
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Applying statistical machine learning to multicore voltage & frequency scaling
Proceedings of the 7th ACM international conference on Computing frontiers
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
An approach to resource-aware co-scheduling for CMPs
Proceedings of the 24th ACM International Conference on Supercomputing
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Consistent runtime thermal prediction and control through workload phase detection
Proceedings of the 47th Design Automation Conference
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Statistical static timing analysis using Markov chain Monte Carlo
Proceedings of the Conference on Design, Automation and Test in Europe
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
MicroFix: Using timing interpolation and delay sensors for power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MemScale: active low-power modes for main memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Exploiting dynamic micro-architecture usage in gate sizing
Microprocessors & Microsystems
Evaluation of dynamic voltage and frequency scaling for stream programs
Proceedings of the 8th ACM International Conference on Computing Frontiers
OS-level power minimization under tight performance constraints in general purpose systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Economic learning for thermal-aware power budgeting in many-core architectures
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Identifying the optimal energy-efficient operating points of parallel workloads
Proceedings of the International Conference on Computer-Aided Design
DreamWeaver: architectural support for deep sleep
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Pack & Cap: adaptive DVFS and thread packing under power caps
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Topology-Aware OpenMP process scheduling
IWOMP'10 Proceedings of the 6th international conference on Beyond Loop Level Parallelism in OpenMP: accelerators, Tasking and more
Evaluating and modeling power consumption of multi-core processors
Proceedings of the 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Power agnostic technique for efficient temperature estimation of multicore embedded systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Power-aware speed scaling in processor sharing systems: Optimality and robustness
Performance Evaluation
Thermal prediction and adaptive control through workload phase detection
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Efficient traffic aware power management in multicore communications processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Computing while charging: building a distributed computing infrastructure using smartphones
Proceedings of the 8th international conference on Emerging networking experiments and technologies
Representative critical reliability paths for low-cost and accurate on-chip aging evaluation
Proceedings of the International Conference on Computer-Aided Design
CoScale: Coordinating CPU and Memory System DVFS in Server Systems
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive reduction of the frequency search space for multi-vdd digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting process variability in voltage/frequency control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation based power and supply voltage management for future RF-powered multi-core smart cards
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Ordering circuit establishment in multiplane NoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Power-aware dynamic memory management on many-core platforms utilizing DVFS
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a popular way for designers to exploit growing transistor budgets. We examine the tradeoffs involved in the choice of both DVFS control scheme and method by which the processor is partitioned into voltage/frequency islands (VFIs). We simulate real multithreaded commercial and scientific workloads, demonstrating the large real-world potential of DVFS for CMPs. Contrary to the conventional wisdom, we find that the benefits of per-core DVFS are not necessarily large enough to overcome the complexity of having many independent VFIs per chip.