Power-aware speed scaling in processor sharing systems: Optimality and robustness

Authors:
Adam Wierman;Lachlan L. H. Andrew;Ao Tang
Affiliations:
Computer Science Department, California Institute of Technology, United States;Centre for Advanced Internet Architectures, Swinburne University of Technology, Australia;School of ECE, Cornell University, United States
Venue:
Performance Evaluation
Year:
2012

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Abstract

Adapting the speed of a processor is an effective method to reduce energy consumption. This paper studies the optimal way to scale speed to balance response time and energy consumption under processor sharing scheduling. It is shown that using a static rate while the system is busy provides nearly optimal performance, but having a wider range of available speeds increases robustness to different traffic loads. In particular, the dynamic speed scaling optimal for Poisson arrivals is also constant-competitive in the worst case. The scheme that equates power consumption with queue occupancy is shown to be 10-competitive when power is cubic in speed.