A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Power-aware scheduling for makespan and flow
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Speed Scaling of Tasks with Precedence Constraints
Theory of Computing Systems
The cost of a cloud: research problems in data center networks
ACM SIGCOMM Computer Communication Review
Dynamic voltage and frequency scaling: the laws of diminishing returns
HotPower'10 Proceedings of the 2010 international conference on Power aware computing and systems
Analyzing performance asymmetric multicore processors for latency sensitive datacenter applications
HotPower'10 Proceedings of the 2010 international conference on Power aware computing and systems
Energy-Efficient algorithms for flow time minimization
STACS'06 Proceedings of the 23rd Annual conference on Theoretical Aspects of Computer Science
Continuous feedback fluid queues
Operations Research Letters
Power-aware speed scaling in processor sharing systems: Optimality and robustness
Performance Evaluation
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In this paper we develop techniques for analyzing and optimizing energy management in multi-core servers with speed scaling capabilities. Our framework incorporates the processor's dynamic power, and it also accounts for other intricate and important power features such as the static (leakage) power and switching overhead between speed levels. Using stochastic fluid models to capture traffic burst dynamics, we propose and study different strategies for adapting the multi-core server speeds based on the observable buffer content, so as to optimize objective functions that balance energy consumption and performance. It is shown that, for a reasonable switching overhead and a small number of thresholds, a substantial efficiency gain is achieved. In addition, the optimal power consumptions of the different strategies are hardly sensitive to perturbations in the input parameters, so that the performance is robust to misspecifications of the system's input traffic.