Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
SPEC CPU2006 benchmark descriptions
ACM SIGARCH Computer Architecture News
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
Design perspectives on 22nm CMOS and beyond
Proceedings of the 46th Annual Design Automation Conference
Device/circuit interactions at 22nm technology node
Proceedings of the 46th Annual Design Automation Conference
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modern high performance microprocessors incorporate an abundance of replicated structural components. Many of these components often experience substantially lower utilization while executing a diverse pool of applications. To recover energy efficiency from the lower utilization, system architects resort to dynamic voltage frequency scaling (DVFS). In this paper, we demonstrate that dynamic adaptations using DVFS are markedly energy inefficient than techniques that design circuits ground up for lower performance. We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation. Our technique is the first of its kind that exploits architectural slack in gate sizing, and leverages on-chip redundancy and slack. We evaluate this circuit-architectural co-optimization framework in a superscalar processor by combining standard cell based gate sizing flows with state-of-the-art architectural simulation. Our results show 17-46% improvement in the datapath energy efficiency over traditional circuit designs incorporating DVFS schemes.