Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Trifecta: a nonspeculative scheme to exploit common, data-dependent subcritical paths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting dynamic micro-architecture usage in gate sizing
Microprocessors & Microsystems
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As transition is being made into 22nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss the challenges of device-circuit-system design at the 22 nm node and present techniques at different levels of design abstraction to meet these challenges. In particular, we discuss different device options for multi-gate FETs. Logic and memory design using multi-gate FETs is also considered. Finally, we briefly discuss process variation tolerant system design methodologies for such scaled technologies.