Design Challenges of Technology Scaling
IEEE Micro
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Exploiting dynamic micro-architecture usage in gate sizing
Microprocessors & Microsystems
Supervised design space exploration by compositional approximation of Pareto sets
Proceedings of the 48th Design Automation Conference
Analysis of modeling approaches for on-chip spiral inductors
International Journal of RF and Microwave Computer-Aided Engineering
Designing for dark silicon: a methodological perspective on energy efficient systems
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A defect-tolerant accelerator for emerging high-performance applications
Proceedings of the 39th Annual International Symposium on Computer Architecture
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
Continuous real-world inputs can open up alternative accelerator designs
Proceedings of the 40th Annual International Symposium on Computer Architecture
21st century digital design tools
Proceedings of the 50th Annual Design Automation Conference
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Neural Network Guided Spatial Fault Resilience in Array Processors
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper presents technology and economic challenges posed by 22nm CMOS and beyond, and how they can be addressed by advances in design technology, validation, and testing, to exploit the benefits of scaling we have enjoyed over the decades.