Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
GPGPU: general purpose computation on graphics hardware
ACM SIGGRAPH 2004 Course Notes
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting dynamic micro-architecture usage in gate sizing
Microprocessors & Microsystems
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
Proceedings of the International Conference on Computer-Aided Design
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Proceedings of the International Conference on Computer-Aided Design
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks
Proceedings of the great lakes symposium on VLSI
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The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques and apply them on simultaneous gate sizing and threshold voltage assignment, which is often employed in practice for performance and power optimization. These techniques are aimed to fully utilize the benefits of GPU through efficient task scheduling and memory organization. Compared to conventional sequential computation, our techniques can provide up to 56x speedup without any sacrifice on solution quality.