An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
GPU friendly fast Poisson solver for structured power grid network analysis
Proceedings of the 46th Annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Taming irregular EDA applications on GPUs
Proceedings of the 2009 International Conference on Computer-Aided Design
Parallel multi-level analytical global placement on graphics processing units
Proceedings of the 2009 International Conference on Computer-Aided Design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern floorplanning based on B*-tree and fast simulated annealing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article, we propose a novel floorplanning algorithm for GPUs. Floorplanning is an inherently sequential algorithm, far from the typical programs suitable for Single-Instruction Multiple-Thread (SIMT)-style concurrency in a GPU. We propose a fundamentally different approach of exploring the floorplan solution space, where we evaluate concurrent moves on a given floorplan. We illustrate several performance optimization techniques for this algorithm in GPUs. To improve the solution quality, we present a comprehensive exploration of the design space, including various techniques to adapt the annealing approach in a GPU. Compared to the sequential algorithm, our techniques achieve 6--188X speedup for a range of MCNC and GSRC benchmarks, while delivering comparable or better solution quality.