Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
A parallel circuit-partitioned algorithm for timing-driven standard cell placement
Journal of Parallel and Distributed Computing
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Cell placement on graphics processing units
Proceedings of the 20th annual conference on Integrated circuits and systems design
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 48th Design Automation Conference
GPU programming for EDA with OpenCL
Proceedings of the International Conference on Computer-Aided Design
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GPU platforms are becoming increasingly attractive for implementing accelerators because they feature a larger number of cores with improved programmability. In this paper, we describe our implementation of a state-of-the-art academic multi-level analytical placer mPL [8] on Nvidia's massively parallel GT200 series platforms. We detail our efforts on performance tuning and optimizations. When compared to software implementation on Intel's recent generation Xeon CPU, the speed of the global placement part of mPL is 15X faster on average using a Tesla C1060 card, with comparable WL. (less than 1% WL degradation on average)