A stable fixed-outline floorplanning method
Proceedings of the 2007 international symposium on Physical design
Large-scale fixed-outline floorplanning design using convex optimization techniques
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Memetic Simulated Annealing for the GPS Surveying Problem
Numerical Analysis and Its Applications
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Multiobjective layout optimization of robotic cellular manufacturing systems
Computers and Industrial Engineering
VLSI floorplanning based on the integration of adaptive search models
Journal of Computer and Systems Sciences International
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation
International Journal of Computer Applications in Technology
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Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern very large scale integration (VLSI) floorplanning typically needs to pack blocks within a fixed die (outline), and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. In this paper, the authors study two types of modern floorplanning problems: 1) fixed-outline floorplanning and 2) bus-driven floorplanning (BDF). This floorplanner uses B*-tree floorplan representation based on fast three-stage simulated annealing (SA) scheme called Fast-SA. For fixed-outline floorplanning, the authors present an adaptive Fast-SA that can dynamically change the weights in the cost function to optimize the wirelength under the outline constraint. Experimental results show that this floorplanner can achieve 100% success rates efficiently for fixed-outline floorplanning with various aspect ratios. For the BDF, the authors explore the feasibility conditions of the B*-tree with the bus constraints, and develop a BDF algorithm based on the conditions and Fast-SA. Experimental results show that this floorplanner obtains much smaller dead space for the floorplanning with hard/soft macro blocks, compared with the most recent work. In particular, this floorplanner is more efficient than the previous works.