B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
International Journal of Computer Applications in Technology
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hybrid Algorithm for Floorplanning Using B*-tree Representation
IITA '09 Proceedings of the 2009 Third International Symposium on Intelligent Information Technology Application - Volume 03
IEEE Transactions on Evolutionary Computation
Modern floorplanning based on B*-tree and fast simulated annealing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hybrid Simulated Annealing Algorithm for Nonslicing VLSI Floorplanning
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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International Journal of Computer Applications in Technology
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International Journal of Computer Applications in Technology
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In the unpredictable recent developments in the application of VLSI technology, CAD tools are important for bringing high system performance. The VLSI floorplanning problem aims to arrange a set of modules on a rectangular chip area so as to optimise an appropriate measure of performance. There are two factors in general when dealing with the floorplanning problem. The first one is to find an appropriate topological representation in the form of a data structure. The second aspect considers the application of a stochastic search method on the representation to find an optimised floorplan. Current VLSI floorplanners must include multiple metrics in their objective function such as area, wire length and temperature parameters. Hence an optimisation engine is necessary for the floorplanning problem that can handle multiple metrics. In this paper, we present a review/tutorial of the optimisation techniques based on B*-Tree representation in VLSI floorplanning that have been recently proposed.