Improving FSM evolution with progressive fitness functions
Proceedings of the 14th ACM Great Lakes symposium on VLSI
This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Genetic algorithms for VLSI micro-cell layout area optimization based on binary tree
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
A genetic programming hyper-heuristic approach for evolving 2-D strip packing heuristics
IEEE Transactions on Evolutionary Computation
A genetic algorithm for VLSI floorplanning using o-tree representation
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation
International Journal of Computer Applications in Technology
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We present a genetic algorithm (GA) that uses a slicing tree construction process for the placement and area optimization of soft modules in very large scale integration floorplan design. We have overcome the serious representational problems usually associated with encoding slicing floorplans into GAs and have obtained excellent (often optimal) results for module sets with up to 100 rectangles. The slicing tree construction process used by our GA to generate the floorplans has a runtime scaling of O(n lg n). This compares very favorably with other recent approaches based on nonslicing floorplans that require much longer runtimes. We demonstrate that our GA outperforms a simulated annealing implementation with the same representation and mutation operators as the GA