Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
GPE: A New Representation for VLSI Floorplan Problem
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Handbook of Algorithms for Physical Design Automation
Handbook of Algorithms for Physical Design Automation
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Memetic Algorithm for VLSI Floorplanning
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Nostradamus: a floorplanner of uncertain designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modern floorplanning based on B*-tree and fast simulated annealing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplan Design for Multimillion Gate FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for Partially Reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A hybrid approach and methods for representing the VLSI floorplanning problem in the form of evolutionary processes based on the integration of adaptive behavior models of biological systems and on composite architectures of solution algorithms are described. This makes it possible to deal with large-scale problems and obtain high-quality results in reasonable time. The floorplan synthesis includes two phases. In the first phase, the cut tree is produced using the genetic techniques; in the second phase, the floorplan is formed using the convolution by the methods of collective adaptation of the tree cut. Variants of circuits with the variable module orientation of fixed or stochastic size are considered. The probability of obtaining an optimal solution is 0.9, and the average deviation of the solutions from the optimal ones is 1%.