Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Random generation of test instances for logic optimizers
DAC '94 Proceedings of the 31st annual Design Automation Conference
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Proceedings of the 1997 international symposium on Physical design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Characterization and parameterized generation of synthetic combinational benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2003 international symposium on Physical design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Evaluation of Placement Techniques for DNA Probe Array Layout
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Trade-off Oriented Placement Tool
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimality and Stability Study of Timing-Driven Placement Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal placement by branch-and-price
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
On whitespace and stability in physical synthesis
Integration, the VLSI Journal
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
VLSI floorplanning based on the integration of adaptive search models
Journal of Computer and Systems Sciences International
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Placement is an important step in the overall IC design process in DSM technologies, as it defines the on-chip interconnects, which have become the bottleneck in determining circuit performance. The rapidly increasing design complexity, combined with the demand for the capability of handling nearly flattened designs for physical hierarchy generation, poses significant challenges to existing placement algorithms. There are very few studies on understanding the optimality and scalability of placement algorithms, due to the limited sizes of existing benchmarks and limited knowledge of optimal solutions. The contribution of this paper includes two parts: 1) We implemented an algorithm for generating synthetic benchmarks that have known optimal wirelengths and can match any given net distribution vector. 2) Using benchmarks of 10K to 2M placeable modules with known optimal solutions, we studied the optimality and scalability of three state-of-the-art placers, Dragon [4], Capo [1], mPL [24] from academia, and one leading edge industrial placer, QPlace [5] from Cadence. For the first time our study reveals the gap between the results produced by these tools versus true optimal solutions. The wirelengths produced by these tools are 1.66 to 2.53 times the optimal in the worst cases, and are 1.46 to 2.38 times the optimal on the average. As for scalability, the average solution quality of each tool deteriorates by an additional 4% to 25% when the problem size increases by a factor of 10. These results indicate significant room for improvement in existing placement algorithms.