Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?
Journal of Electronic Testing: Theory and Applications
Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Flexibility measurement of domain-specific reconfigurable hardware
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A benchmark diagnostic model generation system
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans - Special issue on model-based diagnostics
Product-term-based synthesizable embedded programmable logic cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
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The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more “random” graphs