A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Structural analysis and generation of synthetic digital circuits with memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Architecture generation of customized reconfigurable hardware
Architecture generation of customized reconfigurable hardware
Totem: Custom Reconfigurable Array Generation
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Characterization and parameterized generation of synthetic combinational benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of synthetic sequential benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
EURASIP Journal on Applied Signal Processing
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptivity and self-organization in organic computing systems
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
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Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For these designs, flexibility is also a key issue, since it is the flexibility of reconfigurable hardware that allows it to implement a variety of circuits. Despite its importance, there is not yet an established method to measure flexibility. This paper explores the flexibility testing issue for domain-specific reconfigurable architectures. We discuss the concept of flexibility as it pertains to domain-specific architectures, and propose a flexibility testing technique involving synthetic circuit generation. This technique is then used to compare three different domain-specific architecture generation algorithms, demonstrating that the testing can in fact differentiate between architectures of differing levels of flexibility.