Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?

  • Authors:

  • Mukul R. Prasad;Philip Chong;Kurt Keutzer

  • Affiliations:

  • Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA. mukul@eecs.berkeley.edu;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA. pchong@eecs.berkeley.edu;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA. keutzer@eecs.berkeley.edu

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2001

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Abstract

Empirical observation shows that practically encountered instances of combinational ATPG are efficiently solvable. However, it has been known for more than two decades that ATPG is an NP-complete problem (Ibarra and Sahni, IEEE Transactions on Computers, Vol. C-24, No. 3, pp. 242–249, March 1975). This work is one of the first attempts to reconcile these seemingly disparate results. We introduce the concept of cut-width of a circuit and characterize the complexity of ATPG in terms of this property. We introduce the class of log-bounded width circuits and prove that combinational ATPG is efficiently solvable on members of this class. The class of of log-bounded width circuits is shown to strictly subsume the class of k-bounded circuits introduced by Fujiwara (International Symposium on Fault-Tolerant Computing, June 1988, pp. 64–69). We provide empirical evidence which indicates that an interestingly large class of practical circuits is expected to have log-bounded width, which ensures efficient solution of ATPG on them.