Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?
Journal of Electronic Testing: Theory and Applications
Satisfiability, Branch-Width and Tseitin Tautologies
FOCS '02 Proceedings of the 43rd Symposium on Foundations of Computer Science
Parameterized Complexity
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We consider the problem of equivalence checking of circuits N1,N2 with a common specification (CS). We show that circuits N1 and N2 have a CS iff they can be partitioned into toggle equivalent subcircuits that are connected “in the same way”. Based on this result, we formulate a procedure for checking equivalence of circuits N1 and N2 with specifications S1 and S2. This procedure not only checks equivalence of N1 and N2 but also verifies that S1 and S2 are identical. The complexity of this procedure is linear in specification size and exponential in the value of a specification parameter. Previously we considered specifications parameterized by the size of the largest subcircuit (specification granularity). In this paper we give a more general parameterization based on specification “width”.