Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven placement based on partitioning with dynamic cut-net control
Proceedings of the 37th Annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Important placement considerations for modern VLSI chips
Proceedings of the 2003 international symposium on Physical design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2005 international symposium on Physical design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 international symposium on Physical design
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chip surface on which the gates have been coarsely placed via a standard quadratic solve. In this paper, we introduce a timing-driven grid-warping formulation that incorporates slack-sensitivity-based net weighting. Given inevitable concerns about wirelength and runtime degradation in any timingdriven scheme, we also incorporate a more efficient net model and an integrated local improvement ("rewarping") step. An implementation of these ideas, WARP2, can improve worst-case negative slack by 37% on average, with very modest increases in wirelength and runtime.