ITOP: integrating timing optimization within placement

Authors:
Natarajan Viswanathan;Gi-Joon Nam;Jarrod A. Roy;Zhuo Li;Charles J. Alpert;Shyam Ramji;Chris Chu
Affiliations:
IBM Austin Research Laboratory, Austin, TX, USA;IBM Austin Research Laboratory, Austin, TX, USA;IBM Austin Research Laboratory, Austin, TX, USA;IBM Austin Research Laboratory, Austin, TX, USA;IBM Austin Research Laboratory, Austin, TX, USA;IBM Systems and Technology Group, Hopewell Jn., NY, USA;Iowa State University, Ames, IA, USA
Venue:
Proceedings of the 19th international symposium on Physical design
Year:
2010

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Abstract

Timing-driven placement is a critical step in nanometer-scale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a commonly used technique. This paper shows that such an approach can improve timing, but often degrades wire length and routability. Another problem with existing timing-driven placers is inconsistencies in the definition of timing closure. Approaches using linear programming are forced to make assumptions about the timing models that simplify the problem. To truly do timing-driven placement, the placer must be able to make queries to a real timing analyzer with incremental capabilities. This paper describes an incremental timing-driven placer called ITOP. Using accurate timing from an industrial static timer, ITOP integrates incremental timing closure optimizations like buffering and repowering within placement to improve design timing without degrading wire length and routability. Experimental results on a set of optimized industrial circuit netlists show that ITOP significantly outperforms conventional net-weight based timing-driven placement. In particular, on average, it obtains an improvement of over 47.45%, 9.88% and 5% in the worst slack, total negative slack and wire length as compared to the conventional flow.