Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
An LP-based methodology for improved timing-driven placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
Safe Delay Optimization for Physical Synthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Augmenting disjunctive temporal problems with finite-domain constraints
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 3
Simultaneous gate sizing and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
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A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can also resize) multiple cells simultaneously to smooth critical paths, thereby reducing delay and improving worst negative slack or a figure-of-merit. Our approach offers several key advantages over previous formulations, including the accurate modeling of objectives and constraints in the true timing model, and a guarantee of legality for all cell locations.