Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
New timing and routability driven placement algorithms for FPGA synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Criticality history guided FPGA placement algorithm for timing optimization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Dynamic adjustment of virtual paths in ATM networks
ICCOM'06 Proceedings of the 10th WSEAS international conference on Communications
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A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, heuristic net weights or net budgets are not necessary. Additionally, explicit enumeration of a large number of paths is avoided. The flow begins with a given placement and iteratively extracts timing-critical sub-circuits, optimally places the sub-circuit by LP and applies a timing-driven legalizer. The approach is applied to the FPGA domain and yields an average of 19.6% reduction in clock period of routed MCNC designs versus [6] (with reductions up to 39.5%).