Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic synthesis
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Minimum replication min-cut partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An LP-based methodology for improved timing-driven placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simultaneous placement with clustering and duplication
Proceedings of the 41st annual Design Automation Conference
Postplacement rewiring by exhaustive search for functional symmetries
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-based placement considering uncertainty due to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a set of techniques for placement-coupled, timing-driven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timing-driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second we introduce the Replication Tree which allows us to induce large fanin trees from a given circuit which can then be optimized by the embedder. We have built an optimization engine around these two ideas and report promising results for the FPGA domain including clock period reductions of up to 36% compared with a timing-driven placement from VPR [12] and almost double the average improvement of local replication from [1]. These results are achieved with modest area and runtime overhead.