New algorithms for min-cut replication in partitioned circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Minimum replication min-cut partitioning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Replication for logic bipartitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Cell replication and redundancy elimination during placement for cycle time optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Performance driven multiway partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 international symposium on Physical design
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Replicated partitioning for undirected hypergraphs
Journal of Parallel and Distributed Computing
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Graph partitioning is crucial in multiple-chip design, floorplanning and mapping large logic networks into multiple FPGA's. Replication logic can be used to improve the partitioning. Given a network G with only two-pin nets and a pair of nodes s and t to be separated, we introduce a replication graph and an O(mn log(n2/m)) algorithm for optimum partitioning with replication and without size constraints, where m and n denote the number of nets and the number of nodes in G, respectively. In VLSI designs, each partition has size constraints and the given network contains multiple-pin nets. A heuristic extension is adopted to construct replication graphs with multiple-pin nets. Then we use a directed Fiduccia-Mattheyses algorithm in the constructed replication graph to solve the replication cut problem with size constraints