A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Communication based logic partitioning
EURO-DAC '92 Proceedings of the conference on European design automation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Further improve circuit partitioning using GBAW logic perturbation techniques
Proceedings of the conference on Design, automation and test in Europe
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Circuit partitioning with coupled logic restructuring techniques
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved alternative wiring scheme applying dominator relationship
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Dominator-based partitioning for delay optimization
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Multiple wire reconnections based on implication flow graph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
Traditionally, the circuit partitioning problem is done by first modeling a circuit as a graph and then partitioning is performed on the modeling graph. Using the concept of alternative wires, we propose an efficient method that is able to preserve a local optimal solution in the graph domain while a different graph, representing the same circuit, is generated. When a conventional graph partitioning technique reaches a local optimal solution, our proposed technique generates a different graph that is logically equivalent to the original circuit, and that has equal or better partitioning solution. Faced with a different graph which is newly generated, together with a currently good partitioning solution, a conventional graph partitioning technique may then escape from the local optimum and continue searching for better solutions in a different graph domain. The proposed technique can be combined with almost any graph partitioner. Experiments show encouraging results.