Communication based logic partitioning
EURO-DAC '92 Proceedings of the conference on European design automation
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Analysis of multilevel graph partitioning
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Circuit partitioning with coupled logic restructuring techniques
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Postlayout logic restructuring using alternative wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal min-area min-cut replication in partitioned circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
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