Further improve circuit partitioning using GBAW logic perturbation techniques
Proceedings of the conference on Design, automation and test in Europe
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
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Previous results show that node replication can be used to reduce the number of cut edges substantially in a partitioned circuit. The node replication approach is particularly useful for fully utilizing pin-limited devices such as multiple field-programmable gate array. Hwang and El Gamal [1992, 1995] formulated the min-cut replication problem, which is to determine min-cut replication sets for the components of a k-way partition such that the cut size of the partition is minimized after the replication. They gave an optimal algorithm for finding min-cut replication sets for a k-way partitioned digraph. However their optimal min-cut replication algorithm does not guarantee min-cut replication sets of minimum sizes. Furthermore, their algorithm is not optimal for hypergraphs. In this paper, we optimally solve the min-area min-cut replication problem on digraphs, which is to find min-cut replication sets with the minimum sizes. More important, we give an optimal solution to the hypergraph min-area min-cut replication problem using a much smaller flow network model. We implemented our algorithms in a package called Hyper-MAMC, and interfaced Hyper-MAMC to the TAPIR package. We compared the replication results by Hyper-MAMC with those obtained by MC-Rep in the TAPIR package on the exact same initial partitions of a set of MCNC Partition93 benchmark circuits. On average, Hyper-MAMC produces 57.3% fewer cut nets and runs much faster than MC-Rep