Further improve circuit partitioning using GBAW logic perturbation techniques
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Improved alternative wiring scheme applying dominator relationship
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
ATPG-based logic synthesis: an overview
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Postplacement rewiring by exhaustive search for functional symmetries
ACM Transactions on Design Automation of Electronic Systems (TODAES)
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
Logic synthesis for low power using clock gating and rewiring
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph-based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that limited to 2 edges distant from the target wire.The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version [10, 11], and the CPU time is 200 times faster.We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.