Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Detection of symmetry of Boolean functions represented by ROBDDs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Generalized symmetries in boolean functions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
IEEE Design & Test
Boolean Function Representation Based on Disjoint-Support Decompositions
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Constructive multi-level synthesis by way of functional properties
Constructive multi-level synthesis by way of functional properties
Structural Detection of Symmetries in Boolean Functions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Exploiting structure in symmetry detection for CNF
Proceedings of the 41st annual Design Automation Conference
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Solving difficult instances of Boolean satisfiability in the presence of symmetry
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast computation of symmetries in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast postplacement optimization using functional symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utility of the OpenAccess database in academic research
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Postplacement rewiring by exhaustive search for functional symmetries
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Logical and physical restructuring of fan-in trees
Proceedings of the 19th international symposium on Physical design
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
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Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optimizations must use physical and logic information simultaneously. In this work, we propose new algorithms for rewiring and rebuffering - a post-placement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. These techniques are compatible with separate layout and logic optimizations, and appear independent of them. In particular, when the new optimization is applied before or after detailed placement, it approximately doubles the improvement in wirelength. Our contributions are based on exhaustive search for functional symmetries in sub-circuits consisting of several gates. Our graph-based symmetry finding is more comprehensive than previously known algorithms - it detects permutational and phase-shift symmetries on multiple input and output wires, as well as hybrid symmetries, creating more opportunities for rewiring and rebuffering.