The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Congestion-Aware Logic Synthesis
Proceedings of the conference on Design, automation and test in Europe
Exploiting structure in symmetry detection for CNF
Proceedings of the 41st annual Design Automation Conference
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The nuts and bolts of physical synthesis
Proceedings of the 2007 international workshop on System level interconnect prediction
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast computation of symmetries in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast postplacement optimization using functional symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Depth controlled symmetric function fanin tree restructure
Proceedings of the International Conference on Computer-Aided Design
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A symmetric-function fan-in tree (SFFT) is a fanout-free cone of logic that computes a symmetric function, so that all of the leaf nets in its support set are commutative. Such trees are frequently found in designs, especially when the design originated as two-level logic. These trees are usually created during logic synthesis, when there is no knowledge of the locations of the tree root or of the source gates of the leaf nets. Because of this, large SFFTs present a challenge to placement algorithms. The result is that the tree placements are generally far from optimal, leading to wiring congestion, excess buffering, and timing problems. Restructuring such trees can produce a more placeable and wire-efficient design. In this paper, we propose algorithms to identify and to restructure SFFTs during physical design. The key feature of an SFFT is that it can be implemented with various structures of a uniform set of gates with commutative inputs, i.e. AND, OR, or XOR. Drawing on the flexibility of SFFT logic structures, the proposed tree restructuring algorithm uses existing placement information to rebuild the SFFTs with reduced tree wire lengths. The experimental results demonstrate the efficiency and effectiveness of the algorithms.