Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Logical and physical restructuring of fan-in trees
Proceedings of the 19th international symposium on Physical design
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this era of Deep Sub-Micron (DSM) technologies, the impact ofinterconnects is becoming increasingly important as it relates tointegrated circuit (IC) functionality and performance. In thetraditional top-down IC design flow, interconnect effects are firsttaken into account during logic synthesis by way of wireloadmodels. However, for technologies of 0.25µm and below, thewiring capacitance dominates the gate capacitance and the delayestimation based on fanout and design legacy statistics can behighly inaccurate. In addition, logic block size is no longerdictated solely by total cell area, and is often limited by wiringarea resources. For these reasons, wiring congestion is anextremely important design factor, and should be taken intoconsideration at the earliest possible stages of the design flow. Inthis paper we propose a novel methodology to incorporatecongestion minimization within logic synthesis, and present resultsfor industrial circuits that validate our approach.