Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
SIAM Review
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Integrating floorplanning in data-transfer based high-level synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Meta optimization: improving compiler heuristics with machine learning
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Congestion-Aware Logic Synthesis
Proceedings of the conference on Design, automation and test in Europe
Convex Optimization
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Routing Congestion in VLSI Circuits: Estimation and Optimization
Routing Congestion in VLSI Circuits: Estimation and Optimization
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Automatic memory partitioning and scheduling for throughput and power optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measurements for structural logic synthesis optimizations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture and synthesis for on-chip multicycle communication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-Driven Placement and White Space Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis has been proposed to solve the complexity problem by raising the abstraction level. In this paper, we share our vision that high-level synthesis can potentially help the routability problem as well. We show that many interconnect problems that occur in layout can be avoided or mitigated by adopting a layout-friendly RTL architecture generated from high-level synthesis. We also evaluate some structural metrics that can be used to estimate the routability impact of design decisions in high-level synthesis. Experimental results have demonstrated correlations between the metrics and the routability of the resulting design.