Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
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Proceedings of the 2009 International Conference on Computer-Aided Design
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Proceedings of the 19th international symposium on Physical design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the 2013 ACM international symposium on International symposium on physical design
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
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We present a two-stage congestion-driven placement flow. First, during each refinement stage of our multilevel global placement framework, we replace cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions. Second, after the global placement stage, we allocate appropriate amounts of white space into different regions of the chip according to a congestion map by shifting cut lines in a top-down fashion and apply a detailed placer to legalize the placement and further reduce the half-perimeter wirelength while preserving the distribution of white space. Experimental results show that our placement flow can achieve the best routability with the shortest routed wirelength among publicly available placement tools on IBM v2 benchmarks. Our placer obtains 100% successful routings on 16 IBM v2 benchmarks with shorter routed wirelengths by 3.1% to 24.5% compared to other placement tools. Moreover, our white space allocation approach can significantly improve the routability of placements generated by other placement tools