A new optimization algorithm for the vehicle routing problem with time windows
Operations Research
Branch-And-Price: Column Generation for Solving Huge Integer Programs
Operations Research
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
mPL6: a robust multilevel mixed-size placement engine
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal placement by branch-and-price
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
A parallel branch-and-cut approach for detailed placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-Driven Placement and White Space Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
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Existing detailed placement optimization methods typically involve the use of enumeration to determine the optimal location of a small number of cells. We propose two Mixed Integer Programming (MIP) models that can optimize the detailed placement of more cells efficiently. Compared with existing models, the first proposed model has fewer integer variables. The second proposed model, derived based on Dantzig-Wolfe decomposition principle, is with tighter bounds during its solution. Experimental results show that both models are capable of optimizing in reasonable time the detailed placement of much larger problem instances than existing models. Experiments on large-scale real benchmark circuits also show that detailed placer based on advanced MIP models can effectively reduce half-perimeter wirelengh (HPWL), as well as routed wirelength and vertical vias, of the original placement results generated by enumeration approach.