Linear programming and network flows (2nd ed.)
Linear programming and network flows (2nd ed.)
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
A new optimization algorithm for the vehicle routing problem with time windows
Operations Research
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Time-Indexed Formulations for Machine Scheduling Problems: Column Generation
INFORMS Journal on Computing
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A parallel branch-and-cut approach for detailed placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
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Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected transistors. The placement problem is NP-Complete for even simple metrics.In this paper, we apply techniques developed by the Operations Research (OR) community to the placement problem. Using an Integer Programming (IP) formulation and by applying a "branch-and-price" approach, we are able to optimally solve placement problems that are an order of magnitude larger than those addressed by traditional methods. Our results show that suboptimality is rampant on the small scale, and that there is merit in increasing the size of optimization windows used in detail placement.