Introduction to algorithms
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved cut sequences for partitioning based placement
Proceedings of the 38th annual Design Automation Conference
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reporting of standard cell placement results
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Constructive benchmarking for placement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
Post-layout logic optimization of domino circuits
Proceedings of the 41st annual Design Automation Conference
FastPlace: an analytical placer for mixed-mode designs
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Post-layout logic duplication for synthesis of domino circuits with complex gates
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal placement by branch-and-price
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Postlayout optimization for synthesis of Domino circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
A Relocation Method for Circuit Modifications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An effective approach for large scale floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Optimization of placement solutions for routability
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we present improvements to recursive bisection basedplacement. In contrast to prior work, our horizontal cut lines arenot restricted to row boundaries; this avoids a "narrow region"problem. To support these new cut line positions, a dynamic programmingbased legalization algorithm has been developed. Thecombination of these has improved the stability and lowered thewire lengths produced by our Feng Shui placement tool.On benchmarks derived from industry partitioning examples,our results are close to those of the annealing based tool Dragon,while taking only a fraction of the run time. On synthetic benchmarks,our wire lengths are nearly 23% better than those of Dragon.For both benchmark suites, our results are substantially better thanthose of the recursive bisection based tool Capo and the analyticplacement tool Kraftwerk.