Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2005 international symposium on Physical design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
Very large scale integration (VLSI) fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement approaches is crucial to the development of improved automation tools; unfortunately, publicly available placement benchmarks are outdated, and there are wide variations in their interpretation. In addition, the metrics considered by some academic research have questionable relevance to modern design. At best, poor benchmarks and differences in interpretation result in misunderstandings of the effectiveness of some approaches. At worst, they can motivate research in areas of very little promise, while other areas which have true potential are ignored. In this paper, we expand on work previously presented, describing current standard cell placement benchmarks and illustrating common differences in their interpretation. We also propose specific interpretation methods for traditional objectives, and discuss new metrics which should be considered in modern placement research. Our hope is that by presenting these issues clearly, we can enable more accurate evaluations of placement methods, and improve research efficiency