Post-layout logic duplication for synthesis of domino circuits with complex gates

Authors:
Aiqun Cao;Ruibing Lu;Cheng-Kok Koh
Affiliations:
Synopsys, Inc., Mountain View, CA;Synopsys, Inc., Mountain View, CA;Purdue University, West Lafayette, IN
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

Logic duplication to resolve the logic reconvergent paths problem encountered in Domino logic synthesis is expensive in terms of area and power. In this paper, we propose a combined logic duplication minimization and technology mapping scheme for Domino circuits with complex gates. The logic duplication is performed as a post-layout step as the duplication cost is minimized based on accurate timing information. Experimental results show significant improvements in area, power, and delay.