Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Interconnect Effort - A Unification of Repeater Insertion and Logical Effort
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Post-layout logic duplication for synthesis of domino circuits with complex gates
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and future trend of short-circuit power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay analysis of CMOS gates using modified logical effort model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logical effort model extension to propagation delay representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Timing optimization in logic paths with wires has become an important issue in the VLSI circuit design process. Existing techniques for minimizing delay treat only the relatively rare cases of logic without wires (logical effort) or logic with a long resistive wire (repeater insertion). The techniques described in this paper address the fundamental questions of optimal sizing, the number and location of the gates. The Unified Logical Effort (ULE) method supports fast and precise optimal sizing of gates in the presence of interconnect based on intuitive closed-form expressions. The optimal number of repeaters is determined by the Gate-terminated Sized Repeater Insertion (GSRI) technique, resulting in lower delay as compared to standard repeater insertion methodologies. The Logic Gates as Repeaters (LGR) method is used for optimal wire segmenting and gate location, suggesting a distribution of logic gates over interconnect rather than using logically-redundant repeaters. The combination of these techniques provides solution for a wide variety of design issues.