Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Temperature and voltage aware timing analysis: application to voltage drops
Proceedings of the conference on Design, automation and test in Europe
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
Delay estimation and sizing of CMOS logic using logical effort with slope correction
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing constraints. This is due to the inability of the logical effort model in capturing I/O coupling and input ramp effects that distinguish the transition time from the propagation delay. Using an analytical modeling of the supply current that flows in simple gates during their switching process, this paper introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect. Validation of this model is performed on 130-nm STMicroelectronics technology. A compact representation of CMOS library timing performance is given as a possible application of the proposed model. The choice of sampling points to be used in look-up tables as representative steps of the design range is also discussed