Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Temperature effect on delay for low voltage applications
Proceedings of the conference on Design, automation and test in Europe
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Low-Power CMOS Design
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature dependency in UDSM process
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Transition time modeling in deep submicron CMOS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logical effort model extension to propagation delay representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings.