Low Power Oriented CMOS Circuit Optimization Protocol
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Integration, the VLSI Journal
Temperature and voltage aware timing analysis: application to voltage drops
Proceedings of the conference on Design, automation and test in Europe
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature dependency in UDSM process
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical characterization of library timing performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Formal evaluation of the robustness of dual-rail logic against DPA attacks
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Analysis and improvement of dual rail logic as a countermeasure against DPA
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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As generally recognized, the performance of a CMOS gate, such as propagation delay time or short circuit power dissipation, is strongly affected by the nonzero input signal transition time. This paper presents an analytical model of the transition time of CMOS structures. The authors first develop the model for inverters, considering fast and slow input signal conditions, over a large design range of input-output coupling capacitance and capacitive load. They then extend this model to more complex gates. The validity of the presented model is demonstrated through a comparison with HSPICE simulations on a 0.18 μm CMOS process.