Temperature dependency in UDSM process

Authors:
B. Lasbouygues;Robin Wilson;Nadine Azémard;Philippe Maurine
Affiliations:
STMicroelectronics Design Department, Crolles, France;STMicroelectronics Design Department, Crolles, France;LIRMM, Univ. Montpellier II, (C5506), Montpellier, France;LIRMM, Univ. Montpellier II, (C5506), Montpellier, France
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

Citing 2
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Abstract

In low power UDSM process the use of reduced supply voltage with high threshold voltages may reverse the temperature dependence of designs. In this paper we propose a model to define the true worst Process, Voltage and Temperature conditions to be used to verify a design. This model will provide an accurate worst case definition for high performance designs where standard design margins are not applicable. This model is validated at either cell level or path level on two different 130nm process.