Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

Authors:
Zhangcai Huang;Atsushi Kurokawa;Masanori Hashimoto;Takashi Sato;Minglu Jiang;Yasuaki Inoue
Affiliations:
Fukuoka Industry, Science and Technology Foundation, Fukuoka-shi, Japan and Research Center of Information, Production, and Systems, Waseda University, Kitakyushu-shi, Japan;Sanyo Electric Company, Ltd., Gifu, Japan;Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University, Suita-shi, Japan;Graduate School of Informatics, Kyoto University, Kyoto, Japan;Graduate School of Information, Production, and Systems, Waseda University, Kitakyushu-shi, Japan;Graduate School of Information, Production, and Systems, Waseda University, Kitakyushu-shi, Japan
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.