Short circuit power estimation of static CMOS circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Second Generation Delay Model for Submicron CMOS Process
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new approach to power estimation and reduction in CMOS digital circuits
Integration, the VLSI Journal
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
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We present in this paper a novel alternative for the internal power-dissipation estimation of CMOS structures. A first order macromodeling is developed, considering full submicronic additional effects such as input slew dependency of short-circuit currents and input-to-output coupling. We introduce a novel equivalent capacitance concept allowing a direct and frequency-independent comparison of the different power components. A direct link between fanout and input/output slew is studied in order to derive design-oriented analytical macromodels for the internal power components. Validations are presented by comparing simulated values (HSPICE level 6 foundry model 0.65 μm) of power components to calculated values over a wide range of inverter configurations and control conditions. Discussion is given on a first-order generalization of this macromodel to gates. Evidence is given in terms of fanout and equivalent capacitance ratio of the controlling slope contribution on the internal power-dissipation components